The present invention relates to integrated circuit (IC) assemblies, and more particularly to stacked arrangements for semiconductor dies or chips.
Semiconductor technology has shown a dramatic trend to increases in integrated circuit speed and density with general reduction in device size. Typically integrated circuit chips are assembled into integrated circuit packages by which electrical connections may be made to the integrated circuit from external systems. Without attendant improvements in the packaging of ICs, much of the benefit of high device speed may be lost due to wiring propagation delays and transmission line effects of integrated circuit packages and on circuit board assemblies.
Decoupling capacitors are required in many IC applications. One example of such an application is the need for certain IC devices to be insensitive to being bombarded by ionizing radiation. A basic effect oil the ionizing radiation is to generate electron hole pairs in the semiconductor material. In an IC having a power supply voltage and a ground voltage, the effect of being irradiated is to create a high current flow in the chip between the power supply voltage and the ground voltage. The further effect is for the current flowing from the power supply to encounter inductance in the connecting leads from the power supply. The result is that the on-chip voltage essentially collapses. A solution is to place a capacitor across the IC power supply as close as possible to the IC so that the capacitor is charged to the chip poser supply voltage.
Thus a need exists to provide a packaging arrangement which reduces propagation delays, reduces transmission line effects, provides for effective mounting and connection of decoupling capacitors, and provides more IC function per unit volume of space by increasing chip packaging density.